A DRAM (Dynamic Random Access Memory) as a semiconductor memory has been conventionally used. In recent years, to address higher operating speed of a system, a double data rate method of inputting/outputting data at each of rising and falling of a clock has been adopted. Such semiconductor memory is called as a DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), a DDR2-SDRAM, or a DDR3-SDRAM.
For example, when a system device reads data from the DDR-SDRAM, the DDR-SDRAM outputs read data and a read data strobe signal in synchronization with the read data. A receiving circuit provided in the system device adjusts timing of the strobe signal, and captures the read data based on the adjusted strobe signal.
Generally, a signal line for transmitting the strobe signal to the system device is used as a transmission line for bidirectional communication, and is coupled to a plurality of memories. In this case, each of the memories drives the signal line and transmits the strobe signal in a period in which the read data is output, and does not drive the signal line in the other period. Accordingly, as illustrated in FIG. 16A, a logic of a strobe signal DQS is established in a period effective in capturing the read data, a preamble period prior to a leading rising edge effective in capturing the read data, and a postamble period existing after a last falling edge effective in capturing the read data. However, the strobe signal DQS is put into a high impedance (Hi-Z) state in the other period. When the strobe signal DQS is directly provided to a clock terminal of a latch circuit arranged in the receiving circuit to capture the read data, the read data latched once may be damaged if a pulse is superimposed on the strobe signal DQS in the Hi-Z state.
Japanese Laid-Open Patent Publications No. 2010-250859 and No. 2008-293279 each describe using an internal strobe gate signal to mask the strobe signal DQS in the Hi-Z state, so that the strobe signal DQS in the Hi-Z state is not provided to the latch circuit. According to this method, the internal strobe gate signal is generated so as to shift to an H-potential allowing capture of the strobe signal DQS during the preamble period tRPRE of the strobe signal DQS, and shift to an L-potential inhibiting capture of the strobe signal DQS during the postamble period of the strobe signal DQS.
However, various variation factors, such as input/output characteristics of the system device, transmission line delay, and memory characteristics, exist in a path in which a clock signal CK is transmitted from the system device to the memories and the strobe signal DQS is transmitted from the memories to the receiving circuit. Therefore, a signal delay (flight time) in the path is not uniform. Accordingly, the timing when the strobe signal DQS is transmitted to the receiving circuit is not also uniform. For example, as illustrated in FIG. 16A, a rising edge of the strobe signal DQS may be deviated from a rising edge of the clock signal CK after a lapse of a read latency RL from a read command READ (hereinafter, also referred to as “reference edge RE”). This deviation is defined as tDQSCK. In FIG. 16A, a minimum value of the deviation (phase error) from the reference edge RE is represented as tDQSCKmin, and a maximum value of the deviation (phase error) from the reference edge RE is represented as tDQSCKmax. In the case of tDQSCK of “0”, the rising edge and falling edge of the clock signal CK correspond to the rising edge and falling edge of the strobe signal DQS, respectively. Here, in a memory including a delay locked loop (DLL) circuit such as DDR3-SDRAM, the DLL circuit matches the phase of the strobe signal DQS with the phase of the clock signal CK with high accuracy. Thus, the above-mentioned deviation is small. For example, in the tDQSCK specifications of the DDR3-SDRAM, tDQSCKmin is −500 ps, and tDQSCKmax is +500 ps.
As described above, the timing when the strobe signal DQS is transmitted to the receiving circuit is not uniform. Thus, the timing of the internal strobe gate signal is adjusted in accordance with the flight time so that the rising edge of the internal strobe gate signal (activation timing) comes in the preamble period of the strobe signal DQS. Here, when the deviation is small, as illustrated in FIG. 16B, the leading rising edge following the preamble period tRPRE of the strobe signal DQS may be detected by searching the vicinity of the reference edge RE. Thus, by adjusting the timing such that the internal strobe gate signal DQSG rises at a timing at which the phase is shifted from the phase of the detected leading rising edge by, for example, −180 degrees, the internal strobe gate signal DQSG may be risen in the preamble period tRPRE of the strobe signal DQS.
In recent years, an LPDDR2-SDRAM (Low Power DDR2 SDRAM) that dramatically improves power consumption and data transfer rate of mobile equipment has been developed. However, since the LPDDR2-SDRAM has no DLL circuit that adjusts the phase between the clock signal on the side of the system device and the strobe signal DQS, the output timing of the strobe signal DQS largely varies. In this case, for example, as illustrated in FIG. 17, the memory having no DLL circuit controls the strobe signal DQS based on the reference edge RE of the clock signal CK that rises after a lapse of the read latency RL from the read command READ. In such a memory, tDQSCK is defined as a delay time (phase delay) from the reference edge RE to the leading rising edge of the strobe signal DQS. In FIG. 17, a minimum value of the delay time from the reference edge RE is represented as tDQSCKmin, and a maximum value of the delay time from the reference edge RE is represented as tDQSCKmax. In the tDQSCK specifications of the LPDDR2-SDRAM, tDQSCKmin is +2500 ps, and tDQSCKmax is +5500 ps, which are larger than those of the DDR3-SDRAM by an order of magnitude or larger.
To adjust the timing of the internal strobe gate signal in the LPDDR2-SDRAM, it is required to extend a search range for searching the leading rising edge of the strobe signal DQS. However, as apparent from FIG. 17, a Hi-Z period of the strobe signal DQS (refer to a frame indicated by a broken line) exists in a range from tDQSCKmin to tDQSCKmax. Therefore, when the search range is extended, the strobe signal DQS in the Hi-Z state is captured. Accordingly, there may be a case where the activation timing of the internal strobe gate signal may not be correctly adjusted.
Further, in the LPDDR2-SDRAM, the output timing of the strobe signal DQS varies by ±0.5 cycle time in the cycle time of the clock signal CK even during operation of the system device. Thus, also during the operation of the system device, the timing of the internal strobe gate signal needs to be intermittently adjusted.